1. Field of the Invention
This invention relates to an electrostatic discharge (ESD) protection Circuit for a semiconductor integrated circuit suitable for use in preventing the destruction of internal devices caused by an ESD surge and the likes This invention particularly relates to an ESD protection circuit for a semiconductor integrated circuit of which protection performance has been enhanced.
2. Description of the Related Art
Semiconductor integrated circuits (ICs) are required to be resistant to surge voltage and surge current that are caused by electrostatic discharge (ESD) that is loaded on the input/output pad of IC. In general, to meet this requirement, an ESD protection circuit is connected to the input/output pad of IC. FIG. 1A is a sectional view illustrating the structure of a prior art ESD protection circuit, and FIG. 1B is an equivalent circuit diagram thereof.
Referring now to FIG. 1A, in the prior art ESD protection circuit, a p-type epitaxial layer 102 is deposited onto a p-type semiconductor substrate 101, and an N well NW101 and a P well PW101 are ford on its surface. On the surface of the boundary between the N well NW101 and P well PW1021 an n+ diffusion layer ND102 is formed.
On the surface of the N well NW101, an n+ diffusion layer ND101 is formed apart from the n+ diffusion layer ND102, while a p+ diffusion layer PD101 is formed between the n+ diffusion layer ND102 and n+ diffusion layer ND101. These diffusion layers are electrically isolated from each other by shallow trench isolation (STI) films.
On the other hand, an n+ diffusion layer ND103 is formed apart from the n+ diffusion layer ND102 on the surface of the P well PW101, and a p+ diffusion layer PD102 is formed further away from the n+ diffusion layer ND102 The n+ diffusion layer ND103 and p+ diffusion layer PD102 are electrically isolated by another STI film. A conductive film 104 is formed on a p-type epitaxial layer 102 between the n+ diffusion layer ND102 and n+ diffusion layer ND103 via a gate dielectric film (not shown). An n-channel MOS transistor NMOS is formed by this conductive film 104 serving as the gate electrode, the n+ diffusion layer ND103 as the source and the n+ diffusion layer ND102 as the drain.
An input/output pad I/O is connected to the n+ diffusion layer ND101 and p+ diffusion layer PD101, while the conductive film 104, n+ diffusion layer ND103 and p+ diffusion layer PD102 are connected to a ground terminal GND.
As shown in FIG. 1B, in such an ESD protection circuit, the p+ diffusion layer PD101, N well NW101 and P well PW101 constitute a transistor Tr101, while N well NW101, P well PW101 and n+ diffusion layer ND103 constitute a transistor Tr2. Namely, the p+ diffusion layer PD101, N well NW101, P well PW101 and n+ diffusion layer ND103 constitute a silicon controlled rectifier (SCR). The N well NW101 and P well PW101 have parasitic resistances Rnw and Rpw, respectively.
When a surge positive to the ground terminal GND is applied to the input/output pad I/O, a breakdown occurs between the drain (n+ diffusion layer ND102) and the channel (P well PW101) of the transistor NMOS, and then a trigger current Itrig flows from the n+ diffusion layer ND101 to the ground terminal GND via the N well NW101, n+ diffusion layer ND102 and P well PW101. As a result, the potential of the N well NW101 becomes lower than that of the input/output pad I/O due to the parasitic resistance Rnw parasitizing the N well NW101, and the potential of the P well PW101 becomes higher than that of the ground terminal GND due to the parasitic resistance Rpw parasitizing the P well PW101. Then the SCR, which comprises the p+ diffusion layer PD101, N well NW101, P well PW101 and n+ diffusion layer ND103, is activated. At this time, a large current Iscr flows to the ground terminal GND from the input/output pad I/O. As a result, the urge applied to the input/output pad I/O runs away to the ground terminal without damage of its internal circuit.
Examples of such an ESD protection circuit are disclosed in Japanese Patent Publication Laid-Open No Hei. 10-50494 and Japanese Patent Publication Laid-Open No. Hei. 10-313110, U.S. Pat. No. 5,465,189, and xe2x80x9c1990 Symposium on VLSI Technology 6B-5xe2x80x9d p. 75-76, for example.
FIG. 2A is a sectional view illustrating the structure of another prior art ESD protection circuit, and FIG. 2B is an equivalent circuit diagram thereof. Such a prior art ESD protection circuit is disclosed in U.S. Pat. No. 5,465,189, for example. Referring now to FIGS. 2A and 2B, the n+ diffusion layer ND101 is not connected to the input/output pad I/O but the power supply voltage terminal VDD in this prior art ESD protection circuit. The input/output pad I/O is connected only to the p+ diffusion layer PD101. Except for this difference, this prior art ESD protection circuit has the same structure as that of the prior at ESD protection circuit shown in FIGS. 1A and 1B.
In the above prior art ESD protection circuits, there exists the drain (n+ diffusion layer ND102) of the transistor NMOS between the anode and the cathode of the SCR. Thus the distance Lscr between the anode and cathode becomes rather long, about 2-3 xcexcm, even if the technology of the 0.18 xcexcm-generation is applied to the gate, and a sufficiently good ESD performance is not obtained this is because the discharging capability of the SCR degrades, as distance Lscr becomes longer.
FIG. 3A is a sectional view illustrating the structure of another prior art ESD protection circuit, and FIG. 3B is an equivalent circuit diagram thereof. Referring now to FIGS. 3A and 3B, compared with the prior art ESD protection circuit shown in FIGS. 2A and 2B, an n+ diffusion layer ND104 is formed instead of the transistor NMOS and the p+ diffusion layer PD102, and a device isolation film STI is formed between the p+ diffusion layer PD101 and the n+ diffusion layer ND104. The n+ diffusion layer ND104 is connected to a ground terminal GND. Besides, the N well NW101 extends to beneath the device isolation film STI between the p+ diffusion layer PD101 and the n+ diffusion layer ND104. In the other parts of structure, this prior art ESD protection circuit is the same as the prior art ESD protection circuit shown in FIGS. 2A and 2B.
In the prior art ESD protection circuit shown in FIGS. 3A and 3B, the anode-cathode distance Lacr can be reduced because there is no n+ diffusion layer formed between the N well NW101 and the P well FW101.
However, the prior art ESD protection circuits have the following drawbacks. In the ESD protection circuits shown in FIGS. 1A, 1B and FIGS. 2A, 2B, the breakdown in the boundary between the n+ diffusion layer ND102, that is the drain of the MOS transistor NMOS, and P well PW101 become, the trigger voltage (Vtrig) of the SCR. In this case, the breakdown can be controlled by changing the structure of the MOS transistor NMOS, then, the trigger voltage of the SCR can be set at the value lower than the tolerance voltage of the circuit to be protected (not shown) being connected to the input/output pad I/O. However, the SCR must be large size to achieve the adequate ESD performance because of the poor discharge ability of the SCR due to large distance Lscr. AS the result, the parasitic capacitance of the ESD protection circuit becomes large, so the ESD protection circuit can use for a high-speed interface circuit.
Meanwhile, in the ESD protection circuit shown in FIGS. 3A and 3B, the distance Lscr can be reduced. But in this EST protection circuit, the breakdown in the boundary between the N well NW101 and P well PW101 determines the trigger voltage (Vtrig) of the SCR. The trigger voltage of the SCR cannot be set at the value lower than the tolerance voltage of the circuit to be protected because the breakdown in the boundary between the N well and P well becomes as high as a few tens volts. Thus, the circuit to be protected is destructed before the ESD protection circuit becomes active with breakdown.
It is hard to achieve both of enhance of discharge ability with small distance Lscr and reduction of the trigger voltage in the conventional ESD protection circuit. However, in recent years, the 0.10 xcexcm CMOS technology is adopted in semiconductor circuit and the gate oxide films of MOS transistors comprising the internal circuit is thinner than 2 nm. Then, an ESD protection circuit, having both of higher discharge ability and lower trigger voltage than the conventional one, is requested to protect such a semiconductor integrated circuit.
An object of the present invention is to provide an ESD protection circuit for a semiconductor integrated circuit having both of high discharge ability and low trigger voltage.
An ESD protection circuit for a semiconductor integrated circuit in accordance with the present invention comprises: a 1st-conductivity type semiconductor substrate a 2nd-conductivity type well formed in the semiconductor substrate; a first 1st-conductivity type diffusion layer, being formed in the 2nd-conductivity type well, that is connected to a pad; a first 2nd-conductivity type diffusion layer, being formed in the 2nd-conductivity type well; a second 2nd-conductivity type diffusion layer, formed in a part other than the 2nd-conductivity type well of the semiconductor substrate, that is connected to a reference voltage terminal; and a trigger device having two terminals in which the one terminal is connected to the first 2nd-conductivity type diffusion layer via wiring and in which the other terminal is connected to a reference voltage terminal, for allowing electric current to flow when a voltage higher than a predetermined value is applied between the two terminals.
In the present invention, when a surge positive against the reference voltage terminal is applied to the pad, a voltage is applied to the trigger device through the first 1st-conductivity type diffusion layer, the 2nd-conductivity type well, the first 2nd-conductivity type diffusion layer and the wiring. Then a trigger current flows to the trigger device. As a result, the trigger current acts as a base current of the transistor that consists of the first 1st-conductivity type diffusion layer, 2nd-conductivity type well and 1st-conductivity type semiconductor substrate, the transistor turns on. So, the SCR that consists of the first 1st-conductivity type diffusion layer, 2nd-conductivity type well, 1st-conductivity type semiconductor substrate and the second 2nd-conductivity type diffusion layer turns on, and a large current due to the ESD surge flows toward the reference voltage terminal. The surge loaded on the pad is thereby released.
Also in the present invention, since the trigger device is connected with the wiring to the first 2nd-conductivity type diffusion layer, the trigger device can be located outside the SCR. As a result, the base length of the SCR, this is the distance Lscr, can be reduced, and the ESD performance can be improved. Since the trigger voltage of the SCR can be controlled by changing the characteristics of the trigger device and the trigger device can be designed independently of the SCR, the trigger voltage can be set at an arbitrary value. Then, the ESD protection circuit for a semiconductor integrated circuit having both of high discharge ability and low trigger voltage can be achieved. As a result, the signal voltage applied to the pad has a large margin. Besides, in case of using a circuit to be protected having an extremely thin gate oxide film of the 0.10 xcexcm generation, this circuit can be protected by controlling the trigger voltage to be lower than the tolerance voltage of the circuit. Also, the parasitic capacitance can be reduced because the size of the SCR can be smaller. Then, the ESD protection circuit can use for a high-speed interface circuit.
In the present invention, the pad is connected to the trigger device via the first 1st-conductivity type diffusion layer, 2nd-conductivity type well and the first 2nd-conductivity type diffusion layer but directly, then the possible destruction of the trigger device before turning on the SCR can be prevented.
Also, if a current flows from the pad to the trigger device directly, the current doesn""t flow in a transistor of a SCR, then, the current doesn""t act the base current of the transistor. Contrarily, in the present invention, the current flows from the pad to the base of the transistor, which case the SCR. Then, the SCR can turn-on immediately when the surge is applied to the pad.
According to the present invention, the trigger device can be located outside the SCR, because the trigger device in the ESD protection circuit is connected to the base of the transistor forming the SCR via a metallic wire. Then the length of the base of the SCR can be reduced and the ESD performance is thereby improved. In addition, since the trigger voltage of the SCR can be controlled by changing the characteristics of the trigger device, the trigger voltage can be set at a desired value. As a result, the signal voltage applied to the input/output pad has a large voltage margin. Further, even when a MOS transistor having extremely thin gate oxide film of the 0.10 xcexcm generation is used, the gate oxide films can be protected from destruction.